The present invention generally relates to test clocking schemes, and more specifically relates to a test clocking scheme wherein the memory functional clock is separated from the memory test clock (i.e., two separate clock paths are provided).
With ever-increasing levels of integration, the number of memories and cores used in a design is getting large along with the amount of logic in the rest of the design. Testing these memories and cores means supplying lots of current to the entire chip, often more than the chip is designed to handle in functional mode due to the nature of these tests and the extra logic added for test. Conversely, in functional mode, the chip may be over-burdened by the power requirement of the extra test logic.
While designing the chip, the chip designer may not consider power issues for test, as he is more interested in power issues related to in-system use. Oftentimes, the designer will design the chip such that portions of the chip effectively cut off in certain modes during system use to save power. However, typically power to test logic is not shut off for system use. Furthermore, oftentimes too much power is required for test with both test logic and functional logic powered up.